portal da computação    ciência da computação     engenharia de computação     pós-graduação webmail
por Gerson Cavalheiro, 1 ano, 57 dias atrás

Título: Energy/Quality-Aware Hardware Solutions for the Residual Coding Loop Components of the High Efficiency Video Coding Standard



  • Marcelo Schiavon Porto, Orientador (PPGC-UFPel)

Banca Examinadora:

  • Leomar da Rosa Junior (PPGC-UFPel)
  • Guilherme Ribeiro Correa (PPGC-UFPel)
  • José Luís Almada Güntzel (UFSC)

Data: 5 de Março de 2018

Hora: 10:00

Local: Auditório da Reitoria

Multimedia applications, such as digital videos, are very popular nowadays, especially on mobile devices. Moreover, there is an expectation of continuous growth of the Internet-based digital videos traffic throughout the next years. Video coders, e.g. the High Efficiency Video Coding (HEVC), are very important in this context as the video coders can rationalize Internet resources by reducing the amount of video related data flowing through the network. Unfortunately, this data reduction requires a huge computational effort. Thus, the use of hardware accelerators can be used as a feasible solution, with high-throughput and low-power solutions. The HEVC residual coding loop (RCL), composed by direct transformation, direct quantization, inverse quantization, and inverse transformation, is a highly-requested stage of video coding standards since it is used multiple times to test several coding modes. Therefore, the objective of this work is to provide multiple energy /quality-aware dedicated hardware solutions to increase throughput for the components of RCL in HEVC, allowing real time processing of many encoding modes by the RCL. Thus, the HEVC encoder using the presented solutions is expected to be more coding efficient than the ones using the solution proposed by the existent related works. Innovative solutions are proposed in this work to increase throughput, which has direct impact in the coding efficiency in the RCL components, with low power dissipation. A direct DCT was proposed based on the Fast Fourier Transform (FFT), which allows an intensive hardware reuse, and energy-consumption reduction, able to operate up to 2.54 GHz while dissipation 12.33 mW of power; an energy/quality scalable inverse DCT is presented using a bypass engine based on statistical analysis, setting a trade-off between coding-efficiency and energy-efficiency, which operates up to 737.46 MHz and dissipates between 13.87 mW and 16.84 mW; and a project space exploration of quantization architectures is also presented, with power dissipation of 152.13 mW and 31.15 mW at 888.10 Mhz and 1.36 GHz, respectively, including an integrated direct/inverse quantization, which reduce the number of arithmetical operations by integrating direct quantization and inverse quantization, dissipating 369.37 mW at 1.68 GHz. The developed hardware architectures are able to process up to 108, 32, 38, 58, and 72 coding modes of UHD 4K videos at 60fps for the DCT, IDCT, direct quantization, inverse quantization, and integrated direct/inverse quantization hardware architectures, respectively. When compared with related works, the developed RCL components hardware architectures can operate on higher frequencies, present bigger throughputs, and are more energy efficient.

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